1. Field of the Invention
The present invention relates to a method of fabricating a liquid crystal display device enabling formation a uniform gate silicon nitride insulating layer by increasing the airflow of a mono-silane gas when the gate insulating is being deposited.
2. Discussion of the Related Art
Generally, liquid crystal display devices are widely used because they are compact and thin size as well as light weight. Typically, liquid crystal display devices have a great contrast ratio, and are suitable for both gray scale and moving picture display. In addition, liquid crystal displays consume less power than alternate display, notably CRTs (cathode ray tube).
Such a liquid crystal display device includes a thin film transistor substrate having thin film transistors and pixel electrodes in pixel areas defined by gate and data lines, a color filter substrate having a color filter layer and a common electrode, and a liquid crystal layer inserted between the thin film transistor and color filter substrates.
The typical liquid crystal display generally includes two substrates having electric field generating electrodes formed thereon respectively to confront each other and liquid crystals injected between the two confronting substrates. If a voltage is applied to the electrodes to generate an electric field, liquid crystals molecules are driven to display an image in accordance with light transmittance varied by the electric field.
There are various types of the liquid crystal displays. Recently an active matrix liquid crystal display (AM-LCD) on which thin film transistors and pixel electrodes connected to each other are arranged in a matrix have been receiving heightened attention as they provide excellent resolution and implementation of moving pictures.
Such a liquid crystal display contains pixel and common electrodes that are formed on lower and upper substrates, respectively, and drives the liquid crystal molecules by applying an electric field between the substrates in a direction perpendicular to the substrates.
A liquid crystal display according to a related art is explained by referring to the attached drawings as follows.
Referring to FIG. 1, a plurality of gate lines 11 are formed in one direction on a lower array substrate 10 of a liquid crystal display and a gate electrode 12 protrudes from one side of each of the gate lines 11.
A plurality of data lines 14 are formed perpendicular to the gate lines 11, and cross with the gate lines 11 to define pixel areas, respectively.
A source electrode 15 protrudes from one side of each of the data lines 14, and a drain electrode 16 is separated from the source electrode 15 to leave a predetermined interval.
Moreover, the source, drain, and gate electrodes 15, 16, and 12 form a thin film transistor T including an active layer of amorphous silicon 13 over the gate electrode 12.
The source and drain electrodes 15 and 16 overlap both upper sides of the gate electrode 12.
A pixel electrode 18 made of a transparent conductive material is formed on each of the pixel areas to overlap the drain electrode 16 in part, and a contact hole 17 is formed at the portion where the pixel and drain electrodes 18 and 16 overlap with each other.
Meanwhile, a storage capacitor Cst is formed to maintain a cell voltage.
In this case, an upper electrode of the storage capacitor Cst is formed of an opaque metal layer 14a having a predetermined pattern and a lower electrode of the storage capacitor Cst is formed of the gate line 11 at the front end.
The opaque metal layer 14a is formed to overlap the gate line 11 at the front end in part when the data line 14 is formed, and partially overlaps the pixel electrode 18.
In addition, a contact hole 17a exposing a predetermined portion of the opaque metal layer 14a is formed together with the previous contact hole 17. Hence, the gate line 11, opaque metal layer 14a, and an insulating layer 22 (shown in FIG. 2), which is inserted between the gate line 11 and opaque metal layer 14a, form the storage capacitor Cst when a voltage is applied to the pixel electrode 18.
A storage-on-gate system is shown in the drawing, and a lower electrode of the storage capacitor is integral with the gate line at the front end.
A cross-sectional view of such an array substrate is shown in FIG. 2 illustrating a cross-sectional view along a cutting line V-V′ in FIG. 1, in which a storage electrode part A and a thin film transistor part B are separated from each other for explanation. And, the same elements are indicated by the same numerals.
Referring to FIG. 2, a gate line 11 is formed in the storage electrode part A on a lower array substrate 10 and a gate electrode 12 extending from the gate line 11 is formed in the thin film transistor part B.
A gate insulating layer 22 is formed on an entire surface of the storage electrode and thin film transistor parts A and B.
And, an active layer 13 is formed in a thin film transistor forming area on the gate insulating layer 22 of the thin film transistor part B.
The active layer 13 includes an amorphous silicon layer 13a and a doped semiconductor layer 13b on the amorphous silicon layer 13a for ohmic contact and etch prevention.
Source and drain electrodes 15 and 16 are arranged to overlap both side ends of the doped semiconductor layer 13b, respectively.
In this case, the source electrode 15 is an electrode extending from the data line 14, and the drain electrode 16 is isolated from the source electrode 15.
Besides, an opaque metal layer 14a that overlap the gate line 11 is formed in the storage electrode part A simultaneously when the source and drain electrodes 15 and 16 are formed.
A passivation layer 24 is formed on an entire surface of the substrate 10 having the opaque metal layer 14a and source/drain electrodes 15/16 formed thereon.
Contact holes 17 and 17a exposing predetermined portions of the drain electrode 16 and opaque metal layer 14a respectively are formed in the passivation layer 24. And, a pixel electrode 18 made of a transparent material is formed on the passivation layer 24 in the pixel area to contact the drain electrode 16 and opaque metal layer 14a. 
In the above-constituted liquid crystal display device, the gate insulating and passivation layers 22 and 24 have great influence on the storage capacitance Cst between the gate line 11 and pixel electrode 18.
The storage capacitance Cst plays a role in uniformly maintaining the voltage applied to the pixel electrode 18, and the gate insulating layer 22 is the most important factor that affects electric characteristics of the thin film transistor.
Moreover, the gate insulating layer 22 demands a high insulating characteristic between the gate electrode 12 and active layer 13 while the voltage is not applied thereto, and uses a thin insulating layer material having stable characteristics as well as a good breakdown voltage.
Typically, silicon oxide (SiO2), silicon nitride (SiNx), or the like is widely used to form the gate insulating layer 22.
However, silicon oxide has a slow deposition rate when the layer is formed for fabricating a thin film transistor (TFT) and has a low breakdown voltage for insulation. Hence, the silicon nitride layer is commonly used as the material of the insulating layer.
A method of forming a silicon nitride layer according to a related art is explained as follows.
First of all, the silicon nitride layer is formed by plasma enhanced chemical vapor deposition (PECVD) using a gas mixture of mono-silane (SiH4) and ammonia (NH3).
For instance, the silicon nitride layer is formed by mixing 320 sccm (standard cubic cm/min) of a mono-silane (SiH4) gas and 1,200 sccm of an ammonia (NH3) gas with each other at a mixing ratio of about 0.27:1.
The silicon nitride layer prepared using the mixed raw material gas with the mixing ratio can be used as the gate insulating layer as well as the passivation layer.
In order to form a silicon nitride layer fitting the characteristics of the gate insulating and passivation layers, a more reasonable process of fabricating the silicon nitride layer is demanded.
A process of depositing a silicon nitride layer according to a related art is explained in detail as follows.
FIG. 3 illustrates a diagram of a deposited thickness of a silicon nitride layer according to a related art.
Referring to FIG. 3, a contour line is used in the drawing so that a horizontal direction indicates a horizontal length of a substrate, a vertical direction indicates a vertical length of the substrate, and a height direction indicates a thickness of a silicon nitride layer.
In the drawing, the silicon nitride layer according to the related art is deposited thick in the central portion of the substrate and tends to become thinner toward the edges of the substrate.
Namely, in a single substrate including several liquid crystal cells A, B, C, D, E, and F, as shown in FIG. 4, the silicon nitride layer is deposited thin on peripheries of the liquid crystal cells C, D, E, and F corresponding to both sides of the substrate.
FIG. 5 illustrates a graph of a cross-section along a cutting line I˜I′ in FIG. 3.|
Referring to FIG. 5, a horizontal axis is a horizontal length of a substrate and a vertical axis indicates a measured value of a silicon nitride layer thickness 25.
The silicon nitride layer thickness is measured in units of “Å”. As mentioned in the foregoing explanation, the silicon nitride layer is deposited thick in the central portion of the substrate and becomes thinner toward the edges of the substrate. Hence, a difference in thickness between the central portion and edge of the substrate is about 500 Å.
However, the process of depositing the silicon nitride layer according to the related art has the following problems or disadvantages.
First of all, when the thickness of the silicon nitride layer deposited in the central portion fails to be uniform with that in the edge portion, the gate insulating layer inserted between the gate line and pixel electrode brings about a storage capacitance fluctuation.
Such a storage capacitance fluctuation makes each area differ in capability of maintaining a voltage, whereby an image displayed on a screen fails to disappear the moment power turns off. Specifically, the image on the edge of the substrate in which the silicon nitride layer is thin turns off slowly due to the increased capacitance.
Secondly, the thickness difference in the gate insulating layer brings about a capacitance difference of the thin film transistor.
Such a capacitance difference is mainly affected by the impurities in the gate insulating layer but is an important variable for determining the value of threshold voltage when a channel is formed in the semiconductor layer.
Hence, the deviation according to the thickness of the silicon nitride layer may have influence on the value of threshold voltage.
Finally, the capacitance difference caused by the thickness difference of the gate insulating layer triggers a difference of parasitic capacitance due to the thickness of the gate insulating layer, whereby a data voltage applied to the pixel electrode varies to make the image flicker.